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This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some teststructures design features are provided in JESD87 and in ASTM 1259M - 96.
Author | EIA |
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Editor | EIA |
Document type | Standard |
Format | File |
Confirmation date | 2012-10-01 |
ICS | 33.020 : Telecommunications in general
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Number of pages | 32 |
Replace | EIA JEP 119 (1994) |
Year | 2003 |
Document history | EIA JEP 119A (2003-08) |
Country | USA |
Keyword | EIA 119A;119A;EIA JEP119A |