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EIA JEP 147:2003
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EIA JEP 147:2003
Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA)More info
This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.
| Author | EIA |
|---|---|
| Editor | EIA |
| Document type | Standard |
| Format | File |
| ICS | 31.080.30 : Transistors
|
| Number of pages | 11 |
| Year | 2003 |
| Document history | |
| Country | USA |
| Keyword | EIA 147;147;EIA JEP147 |