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This document describes an accelerated stress and test methodology for measuring device paramete
changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This document gives a procedure to investigate NBTI stress in a symmetric voltage condition with the channel inverted (VGS < 0) and no channel conduction (VDS = 0).There can be NBTI degradation during channel conduction (VGS < 0, VDS < 0), however, this document does not cover this phenomena.
Author | EIA |
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Editor | EIA |
Document type | Standard |
Format | File |
ICS | 31.200 : Integrated circuits. Microelectronics
|
Number of pages | 20 |
Year | 2004 |
Document history | |
Country | USA |
Keyword | EIA 90;90;EIA JESD90 |