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The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used.
| Author | EIA | 
|---|---|
| Editor | EIA | 
| Document type | Standard | 
| Format | File | 
| ICS | 31.080.01 : Semiconductor devices in general | 
| Number of pages | 14 | 
| Replace | EIA JESD 22-B108A (2003-01) | 
| Year | 2010 | 
| Document history | EIA JESD 22-B108B (2010-09) | 
| Country | USA | 
| Keyword | EIA JESD 22;EIA 22;EIA 22.B108B;22;EIA JESD22-B108B |