More info
This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm. An important application of this interface is for in-package, die-to-die interconnection. Inpackage applications may also take advantage of reduced ESD (Electro-Static Discharge) tolerance requirements. This interface may be used in both logic to memory and logic to logic applications. The memory used may be either volatile or non-volatile. This specification only defines interface parameters. The function and interconnection of other parts of the devices is to be defined elsewhere.
| Author | EIA |
|---|---|
| Editor | EIA |
| Document type | Standard |
| Format | File |
| ICS | 35.200 : Interface and interconnection equipment
|
| Number of pages | 10 |
| Year | 2015 |
| Document history | |
| Country | USA |
| Keyword | EIA JESD 8;EIA 8;EIA 8.28;8;EIA JESD8-28 |