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IEEE 1212.1
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IEEE 1212.1 1993 Edition, June 17, 1993 Standard for Communicating Among Processors and Peripherals Using Shared Memory (Direct Memory Access - DMA)
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Description / Abstract:
Foreword
Primitive yet high-performance means are defined for passing messages across the bus between the Processor and some form of intelligence in the I/O Units Function. This message-passing scheme makes minimal demands on the instruction set and hardware required. In addition, several simple conventions are defined for the structure of the messages passed. The intent is to provide a standard architectural framework that supports the detailed definition of application-dependent I/O Unit and Function interface standards. The algorithms and definitions themselves are useful in the design of integrated circuits for I/O.
This document evolved from rough draft documents originally developed within the P1212 Working Group. Work was later moved to a separate working group in order to expedite completion of the IEEE Std 1212-1991 CSR Architecture. It is anticipated that additional documents will be added to the IEEE 1212 series in the future (for example, for standard system boot, specific standard I/O Unit interfaces, etc.) and that standards in other series will also be based on this work.
It is not necessary to read IEEE Std 1212-1991 in order to obtain an overall understanding of the models in this document. Also, many aspects of this framework are expected to be useful in systems that are not compatible with IEEE Std 1212-1991.
Scope of DMA recommendations
This document describes a DMA Framework that provides recommended architectures for high-performance interfaces between Functions1 and System Memory, connected by buses that are generally compatible with the IEEE Std 1212-1991 CSR Architecture,2 such as Futurebus+ [B1] , [B2] and Serial Bus [B4] .3 These buses are characterized by high bandwidth, but have significant delays compared to Processor access to cache, particularly when used to interconnect multiple buses or large numbers of mostly independent units. The design models defined by this DMA Framework assume that transaction latencies could be large. Four models for Processor to I/O Function communication and one model for I/O Function to I/O Function communication are described. Other designs may be appropriate for single-board systems, where the I/O related Function has immediate access to System Memory and Processor resources.
Other DMA architectures are possible in systems conforming to IEEE Std 1212-1991. It must be emphasized that the objective is not to arrive at a single DMA model that will be welded forever to IEEE Std 1212-1991. DMA specifications should be optional to allow for newer and better schemes, or ones more suited to a given application. Yet a point of departure is needed that will guide the initial development of common interfaces.
The approach of this document is to define very primitive yet high-performance means of passing messages across the bus, between the Processor and some form of intelligence in the I/O Units Function (e.g., an I/O card processor or intelligent frontplane chip).4 This message-passing scheme should make minimal demands on the instruction set and hardware required. In addition, several simple conventions are defined for the structure of the messages passed to do common operations in a common way. The most important convention is the vector structure used for representing buffer segments of user data. These message-passing and structure definitions form the building blocks for specific interfaces; for example, LAN, disk, and printer interfaces.
This document is not a complete interface standard. It is a standard architectural framework that supports the detailed definition of application-dependent I/O Unit and Function interface standards, but standard general-purpose bus interfaces and DMA-related hardware, to support one or more of these standards, can be designed that use the primitive definitions of this document.
This framework is recommended to guide system designs. The intention is to maximize inter-vendor compatibility and to maximize the possibility that general-purpose integrated circuits will be available for a wide range of applications.
Primitive yet high-performance means are defined for passing messages across the bus between the Processor and some form of intelligence in the I/O Units Function. This message-passing scheme makes minimal demands on the instruction set and hardware required. In addition, several simple conventions are defined for the structure of the messages passed. The intent is to provide a standard architectural framework that supports the detailed definition of application-dependent I/O Unit and Function interface standards. The algorithms and definitions themselves are useful in the design of integrated circuits for I/O.
This document evolved from rough draft documents originally developed within the P1212 Working Group. Work was later moved to a separate working group in order to expedite completion of the IEEE Std 1212-1991 CSR Architecture. It is anticipated that additional documents will be added to the IEEE 1212 series in the future (for example, for standard system boot, specific standard I/O Unit interfaces, etc.) and that standards in other series will also be based on this work.
It is not necessary to read IEEE Std 1212-1991 in order to obtain an overall understanding of the models in this document. Also, many aspects of this framework are expected to be useful in systems that are not compatible with IEEE Std 1212-1991.
Scope of DMA recommendations
This document describes a DMA Framework that provides recommended architectures for high-performance interfaces between Functions1 and System Memory, connected by buses that are generally compatible with the IEEE Std 1212-1991 CSR Architecture,2 such as Futurebus+ [B1] , [B2] and Serial Bus [B4] .3 These buses are characterized by high bandwidth, but have significant delays compared to Processor access to cache, particularly when used to interconnect multiple buses or large numbers of mostly independent units. The design models defined by this DMA Framework assume that transaction latencies could be large. Four models for Processor to I/O Function communication and one model for I/O Function to I/O Function communication are described. Other designs may be appropriate for single-board systems, where the I/O related Function has immediate access to System Memory and Processor resources.
Other DMA architectures are possible in systems conforming to IEEE Std 1212-1991. It must be emphasized that the objective is not to arrive at a single DMA model that will be welded forever to IEEE Std 1212-1991. DMA specifications should be optional to allow for newer and better schemes, or ones more suited to a given application. Yet a point of departure is needed that will guide the initial development of common interfaces.
The approach of this document is to define very primitive yet high-performance means of passing messages across the bus, between the Processor and some form of intelligence in the I/O Units Function (e.g., an I/O card processor or intelligent frontplane chip).4 This message-passing scheme should make minimal demands on the instruction set and hardware required. In addition, several simple conventions are defined for the structure of the messages passed to do common operations in a common way. The most important convention is the vector structure used for representing buffer segments of user data. These message-passing and structure definitions form the building blocks for specific interfaces; for example, LAN, disk, and printer interfaces.
This document is not a complete interface standard. It is a standard architectural framework that supports the detailed definition of application-dependent I/O Unit and Function interface standards, but standard general-purpose bus interfaces and DMA-related hardware, to support one or more of these standards, can be designed that use the primitive definitions of this document.
This framework is recommended to guide system designs. The intention is to maximize inter-vendor compatibility and to maximize the possibility that general-purpose integrated circuits will be available for a wide range of applications.