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Description / Abstract:
IEEE Std 1500 has developed a standard design-for-testability
method for integrated circuits (ICs) containing embedded
nonmergeable cores. This method is independent of the underlying
functionality of the IC or its individual embedded cores. The
method creates the necessary requirements for the test of such ICs,
while allowing for ease of interoperability of cores that may have
originated from different sources.
Purpose
The aim of IEEE Std 1500 is to provide a consistent scalable
solution to the test reuse challenges specific to the reuse of
nonmergeable cores, while preserving the IP aspects that are often
associated with these cores. This objective is achieved through
provision of a core-centric methodology that enables successful
integration of cores into SoCs.
IEEE Std 1500 provides a bridge between core providers and core
users and also facilitates the automation of test data transfer and
reuse between these two entities via the use of the IEEE P1450.6
CTL. This automation relies on information requirements (the
information model) placed on the core provider to ensure that the
core can be successfully integrated by the core user. The result is
shorter time to market for core providers and core users.
The data transfer and reuse from the core provider to the core
user are based on the premise that the core test data are left
unchanged, while the test protocol is adapted from the IEEE 1500
hardware interface to the SoC.