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IEEE 61691-5
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IEEE 61691-5 2004 Edition, October 1, 2004 Behavioural languages Part 5: VITAL ASIC (application specific integrated circuit) modeling specification
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Description / Abstract:
To provide a standard method of modeling ASICs in VHDL. This
method is aimed at providing efficient, accurate, and tool
independent simulation suitable for large chip-level designs
typical of those which are based on ASICs.
Purpose
Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
Purpose
Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.