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IEEE 61691-4
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IEEE 61691-4 2004 Edition, October 1, 2004 Behavioural languages - Part 4: Verilog hardware description language
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Description / Abstract:
Objectives of this standard
The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains
— The formal syntax and semantics of all Verilog HDL constructs
— The formal syntax and semantics of Standard Delay Format (SDF) constructs
— Simulation system tasks and functions, such as text output display commands
— Compiler directives, such as text substitution macros and simulation time scaling
— The Programming Language Interface (PLI) binding mechanism
— The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines
— Informative usage examples
— Informative delay model for SDF
— Listings of header files for PLI
The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains
— The formal syntax and semantics of all Verilog HDL constructs
— The formal syntax and semantics of Standard Delay Format (SDF) constructs
— Simulation system tasks and functions, such as text output display commands
— Compiler directives, such as text substitution macros and simulation time scaling
— The Programming Language Interface (PLI) binding mechanism
— The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines
— Informative usage examples
— Informative delay model for SDF
— Listings of header files for PLI